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preliminary this is a product that has fixed target specifications but are subject ramtron international corporation to change pending characteri zation results . 1850 ramtron drive, colorado springs, co 80921 (800) 545 - f - ram , (7 19) 481 - 7000 rev. 1.1 www.ramtron.com july 2011 page 1 of 13 fm25 c160c 16kb serial 5v f - ram memory features 16k bi t ferroelectric nonvolatile ram ? organized as 2,048 x 8 bits ? high endurance 1 trillion (10 12 ) read/writes ? 36 year data retention at +75 ? c ? nodelay? writes ? advanced high - relia bility ferroelectric process very fast serial peripheral interface - spi ? up to 20 m hz maximum bus frequency ? direct hardware replacement for eeprom ? spi mode 0 & 3 (cpol, cpha=0,0 & 1,1) sophisticated write protection scheme ? hardware protection ? software protection low power consumption ? 250 ? a active current (1 mhz) ? 4 ? a (typ.) standby current industry standard configuration ? industrial temperature - 40 ? c to +85 ? c ? 8 - pin green/rohs soic ( - g ) description the fm25 c160c is a 16 - kilobit nonvolatile memory employing an advanced ferroelectric p rocess. a ferroelectric random access memory or f - ram is nonvolatile but operates in other respects as a ram. it provides reliable data retention for 36 years while eliminating the complexities, overhead, and system level reliability problems caused by eep rom and other nonvolatile memories. t he fm25 c160c performs write operations at bus speed. no write delays are incurred. data is written to the memory array immediately after it has been successfully transferred to the device. the next bus cycle may comme nce immediately without the need for data polling . the fm25 c160c is capable of supporting up to 10 12 read/write cycle s, or a million times more write cycles than eeprom . these capabilities make the fm25 c160c ideal for nonvolatile memory applications req uiring frequent or rapid writes. examples range from data collection, where the number of write cycles may be critical, to demanding industrial controls where the long write time of eeprom can cause data loss. the fm25 c160c provides substantial benefits to users of serial eeprom, in a hardware drop - in replacement. the fm25 c160c uses the high - speed spi bus, which enhances the high - speed write capability of f - ram technology. the specifications are guaranteed over an industrial temperature range of - 40c to +85c. pin configuration pin name function /cs chip select /wp write protect /hold hold sck serial clock si serial data input so serial data output vdd 5v vss ground ordering information fm25 c160c - g green 8 gr een 8 cs so wp vss vdd hold sck si 1 2 3 4 8 7 6 5
FM25C160C - 16kb 5v spi f - ram rev. 1.1 july 2011 page 2 of 13 figure 1. block diagram pin description pin name i/o pin description /cs input chip select: this active low input activates the device. when high, the device enters low - power standby mod e, ignores other inputs, and all outputs are tri - stated. when low, the device internally activates the sck signal. a falling edge on /cs must occur prior to every op - code. sck input serial clock: all i/o activity is synchronized to the serial clock. inpu ts are latched on the rising edge and outputs occur on the falling edge. since the device is static, the clock frequency may be any value between 0 and 20 m hz and may be interrupted at any time. /hold input hold: the /hold pin is used when the host cpu m ust interrupt a memory operation for another task. when /hold is low, the current operation is suspended. the device ignores any transition on sck or /cs. all transitions on /hold must occur while sck is low. /wp input write protect: this active low pin p revents write operations to the status register. this is critical since other write protection features are controlled through the status register. a complete explanation of write protection is provided on page 6. *note that the function of /wp is differen t from the fm25160. si input serial input: all data is input to the device on this pin. the pin is sampled on the rising edge of sck and is ignored at other times. it should always be driven to a valid logic level to meet i dd specifications. * si may be c onnected to so for a single pin data interface. so output serial output. so is the data output pin. it is driven actively during a read and remains tri - state at all other times including when /hold is low. data transitions are driven on the falling edge o f the serial clock. * so may be connected to si for a single pin data interface. vdd supply supply voltage. 5v vss supply ground instruction decode clock generator control logic write protect instruction register address register counter 256 x 64 fram array 11 data i / o register 8 nonvolatile status register 3 wp cs hold sck so si
FM25C160C - 16kb 5v spi f - ram rev. 1.1 july 2011 page 3 of 13 overview the fm25 c160c is a serial f - ram memory. the memory array is logically organized as 2,048 x 8 and is accessed usi ng an industry standard serial peripheral interface or spi bus. functional operation of the f - ram is similar to serial eeproms. the major difference between the fm25 c160c and a serial eeprom with the same pin - out relates to its superior write performance. this makes the fm25 c160c a drop - in replacement for most 16kb spi eeproms that support modes 0 & 3. memory architecture when accessing the fm25 c160c , the user addresses 2,048 locations each with 8 data bits. these data bits are shifted serially. the address es are accessed using the spi protocol, which includes a chip select (to permit multiple devices on the bus), an op - code and a two - byte address. the upper 5 bits of the address range are ?don?t care? values. the complete address of 11 - bits specifies each b yte address uniquely. most functions of the fm25 c160c either are controlled by the spi interface or are handled automatically by on - board circuitry. the access time for memory operation essentially is zero, beyond the time needed for the serial protocol. that is, the memory is read or written at the speed of the spi bus. unlike an eeprom, it is not necessary to poll the device for a ready condition since writes occur at bus speed. that is, by the time a new bus transaction can be shifted into the part, a write operation will be complete. this is explained in more detail in the interface section below. users expect several obvious system benefits from the fm25 c160c due to its fast write cycle and high endurance as compared with eeprom. however there are l ess obvious benefits as well. for example in a high noise environment, the fast - write operation is less susceptible to corruption than an eeprom since it is completed quickly. by contrast, an eeprom requiring milliseconds to write is vulnerable to noise du ring much of the cycle. note : t he fm25 c160c contains no power management circuits other than a simple internal power - on reset. it is the users responsibility to ensure that vdd is within data sheet tolerances to prevent incorrect operation. it is recomm ended that the part is not powered down with chip enable active. serial peripheral interface C spi bus the fm25 c160c employs a serial peripheral interface (spi) bus. it is specified to operate at speeds up to 20 m hz. this high - speed serial bus provides h igh performance serial communication to a host microcontroller. many common microcontrollers have hardware spi ports allowing a direct interface. it is quite simple to emulate the port using ordinary port pins for microcontrollers that do not. the fm25 c160 c operates in spi mode 0 and 3. the spi interface uses a total of four pins: clock, data - in, data - out, and chip select. a typical system configuration uses one or more fm25 c160c devices with a microcontroller that has a dedicated spi port, as figure 2 il lustrates. note that the clock, data - in, and data - out pins are common among all devices. the chip select and hold pins must be driven separately for each fm 25 c160c device . for a microcontroller that has no dedicated spi bus, a general purpose port may be used. to reduce hardware resources on the controller, it is possible to connect the two data pins (si, so) together and tie off (high) the hold pin. figure 3 shows a configuration that uses only three pins. protocol overview the spi interface is a synchro nous serial interface using clock and data lines. it is intended to support multiple devices on the bus. each device is activated using a chip select. once chip select is activated by the bus master, the fm25 c160c will begin monitoring the clock and data l ines. the relationship between the falling edge of /cs, the clock and data is dictated by the spi mode. the device will make a determination of the spi mode on the falling edge of each chip select. while there are four such modes, the fm25 c160c supports mo des 0 and 3. figure 4 shows the required signal relationships for modes 0 and 3. for both modes, data is clocked into the fm25 c160c on the rising edge of sck and data is expected on the first rising edge after /cs goes active. if the clock begins from a high state, it will fall prior to beginning data transfer in order to create the first rising edge. the spi protocol is controlled by op - codes. these op - codes specify the commands to the part. after /cs is activated the first byte transferred from the bu s master is the op - code. following the op - code, any addresses and data are then transferred. note that the wren and wrdi op - codes are commands with no subsequent data transfer. important: t he /cs pin must go inactive after an operation is complete and bef ore a new op - code can be issued. there is one valid op - code only per active chip select.
FM25C160C - 16kb 5v spi f - ram rev. 1.1 july 2011 page 4 of 13 figure 2. system configuration with spi port figure 3. system configuration without spi port spi mod e 0: cpol=0, cpha=0 spi mode 3: cpol=1, cpha=1 figure 4. spi modes 0 & 3 f m 2 5 c 1 6 0 c m o s i : m a s t e r o u t , s l a v e i n m i s o : m a s t e r i n , s l a v e o u t s s : s l a v e s e l e c t s o s i s c k c s h o l d f m 2 5 c 1 6 0 c s o s i s c k c s h o l d s p i m i c r o c o n t r o l l e r s s 1 s s 2 h o l d 1 h o l d 2 m i s o m o s i s c k m i c r o c o n t r o l l e r f m 2 5 c 1 6 0 c s o s i s c k c s h o l d 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7
FM25C160C - 16kb 5v spi f - ram rev. 1.1 july 2011 page 5 of 13 data transfer all data transfers to and from the fm25 c160c occur in 8 - bit groups. they are synchronized to the clock signal (sck) and they transfer most significant bit (msb) first. serial inputs are clocked in on the rising edge of sck. outputs are driven on the falling edge of sck. command structure there are six commands called op - codes that can be issued by the bus master to the fm25 c160c . they are listed in the table below. these op - codes control the functions performed by the memory. they can be divided into three categories. first, are commands that have no subsequent operations. they perform a single function such as to enabl e a write operation. second are commands followed by one byte, either in or out. they operate on the status register. last are commands for memory transactions followed by address and one or more bytes of data. table 1. op - code commands name description op - code value wren set write enable latch 0000 _ 0110b wrdi write disable 0000 _ 0100b rdsr read status register 0000 _ 0101b wrsr write status register 0000 _ 0001b read read memory data 0000 _ 0011b write write memory data 0000 _ 0010b wren - set write ena ble latch the fm25 c160c will power up with writes disabled. the wren command must be issued prior to any write operation. sending the wren op - code will allow the user to issue subsequent op - codes for write operations. these include writing the status regis ter and writing the memory. sending the wren op - code causes the internal write enable latch to be set. a flag bit in the status register, called wel, indicates the state of the latch. wel=1 indicates that writes are permitted. a write to the status regis ter has no effect on the wel bit. completing any write operation will automatically clear the write - enable latch and prevent further writes without another wren command. figure 5 below illustrates the wren command bus configuration. wrdi - write disable t he wrdi command disables all write activity by clearing the write enable latch. the user can verify that writes are disabled by reading the wel bit in the status register and verifying that wel=0. figure 6 illustrates the wrdi command bus configuration. figure 5. wren bus configuration figure 6. wrdi bus configuration
FM25C160C - 16kb 5v spi f - ram rev. 1.1 july 2011 page 6 of 13 rdsr - read status register the rdsr command allows the bus master to verify the contents of the status register. reading status provides in formation about the current state of the write protection features. following the rdsr op - code, the fm25 c160c will return one byte with the contents of the status register. the status register is described in detail in a later section. wrsr C write statu s register the wrsr command allows the user to select certain write protection features by writing a byte to the status register. prior to issuing a wrsr command, the /wp pin must be high or inactive. note that on the fm25 c160c , /wp only prevents writing t o the status register, not the memory array. prior to sending the wrsr command, the user must send a wren command to enable writes. note that executing a wrsr command is a write operation and therefore clears the write enable latch. the bus timing for rdsr and wrsr are shown below. figure 7. rdsr bus timing figure 8. wrsr bus timing status register & write protection the write protection features of the fm25 c160c are multi - tiered. first, a wre n op - code must be issued prior to any write operation. assuming that writes are enabled using wren, writes to memory are controlled by the status register. as described above, writes to the status register are performed using the wrsr command and subject t o the /wp pin. the status register is organized as follows. table 2. status register bit 7 6 5 4 3 2 1 0 name wpen 0 0 0 bp1 bp0 wel 0 bits 0 and 4 - 6 are fixed at 0 and cannot be modified. note that bit 0 (/rdy in eeproms) is wired low since f - ram writ es have no delay and the memory is never busy . all eeproms use ready to indicate whether a write cycle is complete or not. the wpen, bp1 and bp0 control write protection features. they are nonvolatile (shaded yellow). the wel flag indicates the state of th e write enable latch. this bit is internally set by the wren command and is cleared by terminating a write cycle (/cs high) or by using the wrdi command . bp1 and bp0 are memory block write protection bits. they specify portions of memory that are write p rotected as shown in the following table. table 3. block memory write protection bp1 bp0 protected address range 0 0 none 0 1 600h to 7ffh (upper ?) 1 0 400h to 7ffh (upper ?) 1 1 000h to 7ffh (all)
FM25C160C - 16kb 5v spi f - ram rev. 1.1 july 2011 page 7 of 13 the bp1 and bp0 bits and the write enable latch ar e the only mechanisms that protect the memory from writes. the remaining write protection features protect inadvertent changes to the block protect bits. the wpen bit controls the effect of the hardware /wp pin. when wpen is low, the /wp pin is ignored. when wpen is high, the /wp pin controls write access to the status register. thus the status register is write protected if wpen=1 and /wp=0. this scheme provides a write protection mechanism, which can prevent software from writing the memory under any circumstances. this occurs if the bp1 and bp0 are set to 1, the wpen bit is set to 1, and /wp is set to 0. this occurs because the block protect bits prevent writing memory and the /wp signal in hardware prevents altering the block protect bits (if wpen i s high). therefore in this condition, hardware must be involved in allowing a write operation. the following table summarizes the write protection conditions. table 4. write protection wel wpen /wp protected blocks unprotected blocks status register 0 x x protected protected protected 1 0 x protected unprotected unprotected 1 1 0 protected unprotected protected 1 1 1 protected unprotected unprotected memory operation the spi interface, with its relatively high maximum clock frequency, highlights th e fast write capability of the f - ram technology. unlike spi - bus eeproms, the fm25 c160c can perform sequential writes at bus speed. no page register is needed and any number of sequential writes may be performed. write operation all writes to the memory a rray begin with a wren op - code. the next op - code is the write instruction. this op - code is followed by a two - byte address value. the upper 5 - bits of the address are don?t care. in total, the 11 - bits specify the address of the first byte of the write operat ion. subsequent bytes are data and they are written sequentially. addresses are incremented internally as long as the bus master continues to issue clocks. if the last address of 7ffh is reached, the counter will roll over to 0000h. data is written msb fir st. unlike eeproms, any number of bytes can be written sequentially and each byte is written to memory immediately after it is clocked in (after the 8 th clock). the rising edge of /cs terminates a write op - code operation. read operation after the fallin g edge of /cs, the bus master can issue a read op - code. following this instruction is a two - byte address value. the upper 5 - bits of the address are don?t care. in total, the 11 - bits specify the address of the first byte of the read operation. after the op - code and address are complete, the si line is ignored. the bus master issues 8 clocks, with one bit read out for each. addresses are incremented internally as long as the bus master continues to issue clocks. if the last address of 7ffh is reached, the cou nter will roll over to 0000h. data is read msb first. the rising edge of /cs terminates a read op - code operation. the bus configuration for read and write operations is shown below. hold the /hold pin can be used to interrupt a serial operation without a borting it. if the bus master takes the /hold pin low while sck is low, the current operation will pause. taking the /hold pin high while sck is low will resume an operation. the transitions of /hold must occur while sck is low, but the sck pin can toggle during a hold state.
FM25C160C - 16kb 5v spi f - ram rev. 1.1 july 2011 page 8 of 13 figure 9. memory write figure 10. memory read endurance internally, a f - ram operates with a read and restore mechanism . therefore, endurance cycles are applied for each access : read or write. the f - ram architecture is based on an array of rows and columns. each access causes a cycle for an entire row. in the fm25 c160c , a row is 64 bits wide. every 8 - byte boundary marks the beginning of a new row. endurance can be optimized by ensuring frequently accessed data is located in different rows. regardless, f - ram read and write endurance is effectively unlimited at the 20mhz clock speed. even at 2000 accesses per second to the same row, 15 years time will elapse before 10 12 enduran ce cycles occur .
FM25C160C - 16kb 5v spi f - ram rev. 1.1 july 2011 page 9 of 13 electrical specifications absolute maximum ratings symbol description ratings v dd power supply voltage with respect to v ss - 1.0v to +7.0v v in voltage on any pin with respect to v ss - 1.0v to +7.0v and v in < v dd +1.0v t stg storage tem perature - 55 ? c to + 125 ? c t lead lead temperature (soldering, 10 seconds) 26 0 ? c v esd electrostatic discharge voltage - human body model (aec - q100 - 002 rev. e) - charged device model (aec - q100 - 011 rev. b) - machine model ( a ec - q100 - 003 rev. e ) 4kv 1.25kv 300v package moisture sensitivity level msl - 1 stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only, and the functional operation of the device at these or any other conditi ons above those listed in the operational section of this specification is not implied. exposure to absolute maximum ratings conditions for extended periods may affect device reliabil ity. dc operating conditions (t a = - 40 ? c to + 85 ? c, v dd = 4.5v to 5.5 v unless otherwise specified) symbol parameter min typ max units notes v dd power supply voltage 4.5 5.0 5.5 v i dd vdd supply current @ sck = 1.0 mhz @ sck = 20 .0 mhz 0.25 4 .0 ma ma 1 i sb standby current 4 10 ? a 2 i li input leakage current ? 1 ? a 3 i lo output leakage current ? 1 ? a 3 v il input low voltage - 0.3 0.3 v dd v v ih input high voltage 0.7 v dd v dd + 0.3 v v ol output low voltage @ i ol = 2 ma 0.4 v v oh output high voltage @ i oh = - 2 ma v dd - 0.8 v v hys input hysteresi s 0.05 v dd v 4 notes 1. sck toggling between v dd - 0.3v and v ss , other inputs v ss or v dd - 0.3v. 2. sck = si = /cs=v dd . all inputs v ss or v dd . 3. v in or v out = v ss to v dd . 4. this parameter is characterized but not 100% tested. applies only to /cs and sck pins.
FM25C160C - 16kb 5v spi f - ram rev. 1.1 july 2011 page 10 of 13 ac parameters (t a = - 40 ? c to + 85 ? c, v dd = 4.5v to 5.5v unless otherwise specified) symbol parameter min max units notes f ck sck clock frequency 0 20 mhz t ch clock high time 22 ns 1 t cl clock low time 22 ns 1 t csu chip select setup 10 ns t csh c hip select hold 10 ns t od output disable 20 ns 2 t odv output data valid 20 ns t oh output hold 0 ns t d deselect time 60 ns t r data in rise time 50 n s 1,3 t f data in fall time 50 n s 1,3 t su data setup time 5 ns t h data hold time 5 ns t hs /hold setup time 10 ns t hh /hold hold time 10 ns t hz /hold low to hi - z 20 ns 2 t lz /hold high to data active 20 ns 2 notes 1. t ch + t cl = 1/f ck . 2. r ise and fall times measured between 10% and 90% of waveform. 3. this parameter is characterized and n ot 100% tested. capacitance ( t a = 25 ? c, f=1.0 mhz, v dd = 5v) symbol parameter max units notes c o output c apacitance (so) 8 pf 1 c i input c apacitance 6 pf 1 notes 1. this parameter is characterized and not 100% tested. ac test conditions input pulse le vels 10% and 90% of v dd input rise and fall times 5 ns input and output timing levels 0.5 v dd output load capacitance 30 pf data retention symbol parameter min max units notes t dr @ +85oc 10 - years @ +80oc 18 - years @ +75oc 36 - years
FM25C160C - 16kb 5v spi f - ram rev. 1.1 july 2011 page 11 of 13 serial data bus timing /hold timing power cycle timing power cycle timing ( t a = - 40 ? c to + 85 ? c, v dd = 4.5v to 5.5v unless otherwise specified ) symbol parameter min max units notes t pu v dd (min) to first access start 1 - m s t pd last access complete to v dd (min) 0 - ? s t v r v dd rise time 3 0 - ? s/v 1 t vf v dd fall time 10 0 - ? s/v 1 notes 1. sl ope measured at any point on v dd waveform . cs sck si so 1 / tck tcl tch tcsh todv toh tod tcsu tsu th td tr tf cs sck so hold ths thh thz tlz ths thh v d d m i n t p u v d d c s t v r t p d t v f
FM25C160C - 16kb 5v spi f - ram rev. 1.1 july 2011 page 12 of 13 mechanical drawing (8 - pin soic C jedec ms - 012, variation aa) refer to jedec ms - 012 for complete dimensions and notes. all dimensions in millimeters . soic package marking scheme legend: xx xxx xx= part number, p= package type (g=soic) r=rev code, lllllll= lot code ri c=ramtron int?l corp, yy=year, ww=work week example: fm25 c160c , green soic package, year 2010, work week 51 fm 25 c160c g a 00002g1 ric10 51 xxxx xxx p r ll llll l ricyyww pin 1 3 . 90 0 . 10 6 . 00 0 . 20 4 . 90 0 . 10 0 . 10 0 . 25 1 . 35 1 . 75 0 . 33 0 . 51 1 . 27 0 . 10 mm 0 . 25 0 . 50 45 ? 0 . 40 1 . 27 0 . 19 0 . 25 0 ? - 8 ? recommended pcb footprint 7 . 70 0 . 65 1 . 27 2 . 00 3 . 70
FM25C160C - 16kb 5v spi f - ram rev. 1.1 july 2011 page 13 of 13 revision history revision date summary 1.0 3/22/2011 initial release 1.1 7 / 18 /2011 added esd ratings.

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